1. Field of the Invention
This invention relates generally to the field of digital interface design and, more particularly, to a system for controlling and timing the propagation of a digital signal.
2. Description of the Related Art
The design of interfaces plays a significant role in the implementation of many digital systems. One example of a digital system is a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) system. FIG. 1 illustrates a common implementation of a DDR SDRAM system configured on a printed circuit board and comprising a DDR SDRAM Controller coupled to a DDR SDRAM unit through an interface unit (Memory I/O), wherein the Memory I/O is coupled to the DDR SDRAM unit through a set of pad circuits. In a DDR SDRAM, read-data is accompanied by a corresponding trigger signal, commonly referred to as a DQS signal. The DQS signal is commonly used by a host system, which may include an Application Specific Integrated Circuit (ASIC) coupled to the DDR SDRAM through an interface unit such as the Memory I/O, to sample and latch the read-data. The DQS signal does not always assume a distinctly defined low state or high state, considered valid states by the ASIC, during operations that are affected by the DQS signal, but frequently assumes a high impedance state, or stays at a mid-supply level, considered invalid states by the ASIC during the aforementioned operations. The ASIC uses the DQS signal to capture the read-data. The ASIC also typically needs to ascertain when the DQS signal resides in a valid state.
In current low-speed designs the ASIC may use internal timers to determine when the DQS signal is valid. Variations in delay due to process, voltage and temperature make this method very difficult to use for high-speed designs. Current solutions for high-speed systems focus on the design of special pad cells that are used in coupling the Interface unit to the DDR SDRAM. These special pad cells contain digital and analog (mixed-signal) circuit elements used in preventing the DQS signal from propagating inside the ASIC when the DQS signal resides in an invalid state. Such pad cells may require extensive design times and often result in larger than desired cell areas. Most of the time they are also slower than standard pad cells, thus degrading the overall performance of the ASIC in such instances. Therefore, there exists a need for a system and method for controlling the propagation of a signal such as the DQS signal, and like signals, which provide a simple and inexpensive solution while tracking all delay variations that the circuit experiences during operation, without requiring the design of special pad cells.